Abstract
SayLess is a real-time voice digit and speaker recognition system implemented on an DE0-Nano- SoC FPGA using a NiosV (RISC-V) soft processor. The system captures a spoken digit (0–9) through a microphone, runs a complete machine learning inference pipeline in C on-chip, and displays both the recognized digit and the identified speaker on the 7-segment display - all without any cloud connectivity or external compute. The original project proposal described a fully hardware-only voice authentication system implemented in pure SystemVerilog, using Zero-Crossing Rate (ZCR) frequency matching against an enrolled passphrase. The final delivered system differs substantially from that proposal: the scope evolved from hardware-only authentication into a hybrid hardware/software classification system, incorporating a MATLAB-trained machine learning model (PCA + LDA) exported as a C header file and executed by the soft processor. Speaker identification was added as a bonus feature and was not required in the original proposal. This report documents what was originally planned, what changed and why, the complete architecture and algorithm, MATLAB training pipeline, accuracy results, and hardware implementation.